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This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
Ultra-low power systems and circuits are increasingly pivotal for many fast growing segments of semiconductor industry. A confluence of multiple technologies has brought the promising opportunity for pervasive connectivity of people and things closer than ever. Innovative system partitioning, advances in analog and digital circuit design, modern embedded sensing technologies and intelligent power...
Conventional machine vision faces a fundamental latency-power tradeoff, where decreasing latency means increasing frame rate and power consumption. The communication by spikes in the brain provides the inspiration for developments of event-based vision sensors and processing, which could avoid this tradeoff entirely. This paper provides a personal perspective on developments of event-based vision...
Digital technologies are key for the advent and growth of Internet of Things. For the devices closest to the users, they must show performances criteria different than from than needed in pure computing-intensive applications. In particular, the ability to mix digital edge performances with RF or sensor capabilities is key, and some well-adapted technologies, such as FD-SOI, are detailed in the present...
Quantum computers have the potential to revolutionize information technology as we know it by solving certain relevant and interesting problems, using fundamentally fewer resources (number of computational steps) compared with even the fastest supercomputers. While critical aspects of quantum computing are being demonstrated in laboratories across the world, a fully functional and practical quantum...
New concepts in materials science and mechanics design principles provide routes to high performance electronics with physical characteristics matched to those of vital organs of the human body. The resulting opportunities for integration of sensors, actuators, radios and computing capabilities directly on the surfaces or into the depths of targeted tissues have strong potential to improve current...
This paper presents the use of wireless sensor network (WSN) technologies in a newly growing application space in industrial Internet or industry 4.0. This application space focuses on factory automation and field process management that we call Machine Area Network (MAN) applications. We describe key requirements, major technical challenges and how hardware and software can be combined to address...
This paper presents an energy efficiency improvement methodology based on the use of additional static biasing instead of margins during design stage. While the impact of margins used to prevent unsystematic process limitations cannot be recovered after fabrication, using biasing anticipation offers the possibility to enable the degradation recovery only when it is required. A CAD study on ARM Cortex...
A 32-bit icyflex2 processor operating over a wide supply range (WSR) is presented, showing a very low energy consumption in comparison to other state-of-art 32-bit processors. Operating under very different supply conditions involves tremendous differences in operating frequency, and a large sensitivity to process and temperature variations at low-voltage, which both tend to complicate timing closure...
This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power...
We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO2 (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device...
In this paper, we study the impact of material parameters (i.e. effective mass and bandgap) for two-dimensional (2D) material based tunneling FETs (TFETs) on circuit level metrics. We estimate circuit level metrics (i.e delay and energy consumption) of 2D TFETs at different target OFF current (IOFF) for various combination of material parameters. To fulfill a given IOFF requirement for circuit level...
We present the implementation and experimental verification of the first complete digital logic library based on amorphous carbon (a-C)-coated curved-cantilever nanoelectromechanical (NEM) switch technology. Experimental results for sequential gates - latches and edge-triggered D flip-flops (DFF) - and combinational circuits (NAND, AND) are reported for the first time. The capability of the fabricated...
While RF transistor amplifiers—such as the field effect transistor (FET) amplifier which leverages its transconductance for amplification—are the key enablers of signal amplification in today's wireless communication; their ability to provide amplification degrades with increasing frequencies, thereby requiring multiple amplification stages which makes the device noisy, expensive and bigger in size...
For 1.0V operation NAND flash memory, heterogeneously integrated voltage generator is proposed and experimentally demonstrated. The proposed 2-stage boost converter uses high voltage (HV) transistors of standard CMOS process as the 1st stage and HV transistors of NAND flash process as the 2nd stage. The intermediate load capacitance is adaptively adjusted according to the number of NAND flash chips...
We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in...
3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.
This paper presents an AM detector circuit in a bendable a-IGZO TFT technology. The circuit is based on a common-source stage loaded with a single-ended active inductor, which uses only one active transistor. This active inductor is the key element for the achieved circuit performance. The detector circuit consumes only 0.39 mW, which is almost a tenfold improvement over previous works in the same...
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